Welcome to IEEE TCCA Email-Monthly, June 2002: 1. HPCA Website: Special messages from TCCA Chairs submitted by: Jean-Luc Gaudiot, TCCA Chair Josep Torrellas, Vice-chair 2. HPCA9: 9th International Symposium on High Performance Computer Architecture submitted by: Soner Onder Call for Papers: http://www.cs.arizona.edu/hpca9/ 3. DSN2002: 2002 Int'l Conf. on Dependable Systems & Networks (23-26 June 2002) submitted by: Dr. Jaynarayan H. Lala Advance Program: www.dsn.org 4. ASAP'2002: IEEE International Conference on Application-specific Systems, Architectures and Processors, (July 17-19, 2002) submitted by: Mainak Sen Call for participation: http://www.cse.lehigh.edu/ASAP * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members, send an email to tcca@ele.uri.edu * To subscribe/unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: subscribe/unsubscribe ----------------------------------------------------------------------- Qing (Ken) Yang, Professor Distinguished Engineering Professor e-mail: qyang@ele.uri.edu Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 University of Rhode Island Fax (401) 782-6422 Kingston RI. 02881 http://www.ele.uri.edu/~qyang ------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------------ *----------------------------------------------------------------------- * * * HPCA-9 * * * * Call for Papers * * * * Ninth International Symposium on High Performance * * Computer Architecture * * * * Anaheim, California. Feb. 8-12, 2003 * * * * http://www.cs.arizona.edu/hpca9/ * * * * * * Important Dates * * * * Paper submission deadline : July 12, 2002 * * Workshop proposals due : July 12, 2002 * * Author Notification : Oct. 1, 2002 * * Camera ready copy due : Nov. 3, 2002 * * * *----------------------------------------------------------------------- The International Symposium on High-Performance Computer Architecture provides a high quality forum for scientists and engineers to present their latest research findings in this rapidly changing field. Authors are invited to submit full papers on all aspects of high-performance computer architecture. Topics of interest include, but are not limited to: * Processor architectures * Cache and memory architectures * Parallel computer architectures * Impact of VLSI scaling techniques * Novel architectures for emerging applications * Power-efficient architectures * High-availability architectures * High-performance I/O architectures * Embedded and reconfigurable architectures * Real-time architectures * Interconnection networks and network interfaces * Innovative hardware/software trade-offs * Simulation and performance evaluation * Benchmarking and measurements Please check the following web site for paper submission information: http://www.cs.arizona.edu/hpca9/ The submission should not exceed 6000 words. Papers that exceed the length limit or that cannot be viewed using Adobe Acrobat Reader (version 3.0 or higher) may not be reviewed. The official submission deadline is July 12, 2002 (Midnight EST, USA). An automatic extension of one week will be given without request. No further extensions will be given. Papers may be submitted for blind review at the option of the authors. Please indicate whether the paper is a student paper for best student paper nominations. Please submit proposals for workshops to the workshop chair by July 12, 2002. Important Dates Paper submission deadline : July 12, 2002 Workshop proposals due : July 12, 2002 Author Notification : Oct. 1, 2002 Camera ready copy due : Nov. 3, 2002 General Chairs Nader Bagherzadeh, Univ. of California, Irvine Laxmi N. Bhuyan, Univ. of California, Riverside Steering Committee Dharma P. Agrawal, Univ. of Cincinnati Laxmi N. Bhuyan, Univ. of California, Riverside Yale Patt, Univ. of Texas at Austin Jean-Luc Gaudiot, Univ. of California, Irvine Joel Emer, Intel David Kaeli, Northeastern Univ. Pen-Chung Yew, Univ. of Minnesota David Lilja, Univ. of Minnesota Program Chair Rajiv Gupta, Univ. of Arizona Program Committee Todd Austin, Univ. of Michigan Pradip Bose, IBM Doug Burger, Univ. of Texas at Austin Brad Calder, Univ. of California, San Diego Dan Connors, Univ. of Colorado Tom Conte, NC State Univ. Darren Cronquist, HP Labs Chita Das, Penn State Univ. Sandhya Dwarkadas, Univ. of Rochester Marius Evers, AMD Kanad Ghose, SUNY Binghamton Antonio Gonzalez, UPC, Barcelona James Goodman, Univ. of Wisconsin Wei-Chung Hsu, Univ. of Minnesota Yiming Hu, Univ. of Cincinnati Stephen Jenks, Univ. of California, Irvine Steve Melvin, Flowstorm Walid Najjar, Univ. of California, Riverside Soner Onder, Michigan Technological Univ. Santosh Pande, Georgia Tech Sanjay Patel, UIUC Li-Shiuan Peh, Princeton University Timothy Mark Pinkston, USC Ronny Ronen, Intel, Israel John Shen, Intel, MRL Josep Torrellas, UIUC Mateo Valero, UPC, Barcelona Jie Wu, Florida Atlantic Univ. Yuanyuan Yang, SUNY at Stony Brook Local Arrangements Chair Stephen Jenks, Univ. of California, Irvine Workshop Chair Walid Najjar, Univ. of California, Riverside Publications Chair Li-Shiuan Peh, Princeton Univ. Finance and Registration Chair Nayla Nassif, Univ. of California, Irvine Publicity Chair Soner Onder, Michigan Technological Univ. ------------------------------------------------------ ======================================================================= DSN 2002 2002 International Conference of Dependable Systems and Networks Hyatt Regency, Bethesda, MD 23-26 June 2002 www.dsn.org REMINDER: ADVANCE REGISTRATION DEADLINE: 31 May 2002 ======================================================================= Advance program, registration and accommodation information are now available at www.dsn.org. The early registration deadline is May 31, 2002. A block of rooms at the Hyatt Regency has also been blocked till May 31. Plan now to attend the premiere conference on dependable systems and networks, in the capital region of USA, filled with museums, monuments and many more historic attractions. This year's keynote speaker is the Honorable Richard Russell, Associate Director (Designate), White House Office of Science and Technology Policy (OSTP). Computer systems and communications networks now pervade every aspect of our daily lives. While that has benefited society and increased our productivity, it has also made our lives more critically dependent on their correct functioning. The traditional concerns of the dependability community (e.g., inadvertent faults, errors, and failures) have now been enlarged by the massive connectivity provided by the Internet to include malicious exploitation of imperfect systems and networks and intentional cyber-attacks on them. How can we build systems that are not vulnerable to such threats - systems that users can depend upon in defense, transportation, financial, and e-commerce sectors? After 9-11, these questions have taken on even added importance. We have put together an excellent technical program for researchers, practitioners, and users to learn and exchange information on the latest research results and operational systems experiences in dependable systems and networks. There are multiple tracks that include Dependable Computing and Communications, the International Performance and Dependability Symposium, as well as several Workshops and Tutorials, a Student Forum, and late-breaking research. There will also be an excellent social setting to network and mingle, including a reception, lunches, frequent breaks, and a dinner/cruise on the Potomac. ------------------------------------------------------------------------ ASAP'2002 IEEE International Conference on Application-specific Systems, Architectures and Processors July 17-19, 2002 San Jose', California CALL FOR PARTICIPATION This year's ASAP conference includes a rich set of topics and outstanding papers by distinguished authors. Topics covered include design methodologies, low power design, computer arithmetic, memory organization, media processors, cryptography, VLSI architectures, and application-specific system design. In addition to 36 contributed papers, the conference features a keynote address by Dr. Jose' Fortes on "Nanocomputing with Delays." Dr. Fortes is a Professor, BellSouth Eminent Scholar, and Director of the Advanced Computing and Information Systems Laboratory at the University of Florida. The program for the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2002) is available from the conference web page at: http://www.cse.lehigh.edu/ASAP/ The conference features a best paper award. The conference web page also links to (1) The Conference Program (2) Conference Registration - Advance registration ends June 26, 2002 (3) Hotel Information - Reservations can be made through June 25, 2002 (4) Travel Information - Special discounts are available through United Airlines. If you have any questions, please send email to asap@cse.lehigh.edu. We look forward to seeing you at ASAP 2002! -------------------------------------------------------------------------- * To subscribe/unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: subscribe/unsubscribe This is the addendum to the TCCA Email-Monthly, June 2002 ----------------------------------------- 1. New papers published by Computer Architecture Letters Submitted by Kevin Skadron, Associate Editor-in-Chief Website: http://www.cs.virginia.edu/~tcca/ 2. IPDPS 2003, 17th Annual International Parallel and Distributed Processing Symposium Submitted by David A. Bader Call for papers: http://www.ipdps.org/ *Archive: http://www.ele.uri.edu/tcca *To submit an email message to be distributed among TCCA members, send an email to tcca@ele.uri.edu * To subscribe/unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: subscribe/unsubscribe ----------------------------------------------------------------------- Qing (Ken) Yang, Professor Distinguished Engineering Professor e-mail: qyang@ele.uri.edu Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 University of Rhode Island Fax (401) 782-6422 Kingston RI. 02881 http://www.ele.uri.edu/~qyang ------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------- Subject: New papers published by Computer Architecture Letters Message text ------------ Dear TCCA membership: We are delighted to announce the online publication of the next set of four papers in TCCA's new publication, Computer Architecture Letters. "Letters" is a quarterly forum for fast publication of new, high-quality ideas in the form of short, critically refereed, technical papers. Accepted letters are published immediately on our website and in the next available paper issue; the next print issue should arrive in July. Submissions are accepted on a continuing basis. Current turn-around time is 32 days, and we hope to improve this as our review process becomes more efficient. Current acceptance rate is 19%. The titles and abstracts of the new set of letters appears below, and these letters as well as the call for papers and submission instructions, can be found on the Letters website at http://www.cs.virginia.edu/~tcca/ We hope that you will look forward to each issue as a nice digest of some of the latest hot research going on in our field, and we hope that you will submit your early and exciting research results to Letters. We hope that the quick turn-around will encourage this by providing immediate recognition. Since IEEE allows publication in its conferences and journals if there is at least 30% new material and this seems to be a fairly common rule of thumb, this should not constrain researchers from following their letter with full conference papers or journal articles. The kind of paper that we are seeking is an early, "wow" idea that may not yet be ready for a full conference publication, but has enough validated insights to justify publication as a four-page letter. We recognize that some authors may prefer to take the extra time to solidify the research for publication at a prestigious conference rather than risk losing the idea to someone who takes the Letters paper and runs faster with it than the original author. We encourage you to not succumb to that mentality, but rather to submit your new work and get "credit" for the seminal idea, regardless of the outcome of subsequent conference submissions, Since we expect each issue of Letters to contain approximately 16 to 24 pages of really new stuff and will be read by a large fraction of the computer architecture community, credit for the seminal idea is almost guaranteed. We suggest that the seminal idea on one's CV is more valuable than the turn-the-crank-with-lots-of-data papers that we seem to encounter too frequently in the major conferences and journals. It remains, of course, for the community at large to validate this thesis. Yale Patt, Editor-in-Chief Kevin Skadron, Associate Editor-in-Chief Jean-Luc Gaudiot, TCCA Chair New papers, volume 1, 2002, available online at http://www.cs.virginia.edu/~tcca/ ----------------------------------------------- - L. Shang, L.-S. Peh, N. K. Jha. "Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links." Volume 1, May 2002. - O. S. Unsal, I. Koren, C. M. Krishna, C. A. Moritz. "Cool-Fetch: Compiler-Enabled Power-Aware Fetch Throttling." Volume 1, Apr. 2002. - AJ KleinOsowski, D.J. Lilja. "MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research." Volume 1, May 2002. - H. Vandierendonck, K. De Bosschere. "An Address Transformation Combining Block- and Word-Interleaving." Volume 1, May 2002. Abstracts --------- - L. Shang, L.-S. Peh, N. K. Jha. "Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links." Volume 1, May 2002. Power consumption is a key issue in high-performance interconnection network design. Communication links, already a significant consumer of power now, will take up an ever larger portion of the power budget as demand for network bandwidth increases. In this paper, we motivate the use of dynamic voltage scaling (DVS) for links, where the frequency and voltage of links are dynamically adjusted to minimize power consumption. We propose a history-based DVS algorithm that judiciously adjusts DVS policies based on past link utilization. Despite very conservative assumptions about DVS link characteristics, our approach realizes up to 4.3X power savings (3.2X average), with just an average 27.4% latency increase and 2.5% throughput reduction. To the best of our knowledge, this is the first study that targets dynamic power optimization of interconnection networks. - O. S. Unsal, I. Koren, C. M. Krishna, C. A. Moritz. "Cool-Fetch: Compiler-Enabled Power-Aware Fetch Throttling." Volume 1, Apr. 2002. In this paper, we present an architecture-compiler based approach to reduce energy consumption in the processor. While we mainly target the fetch unit, an important side-effect of our approach is that we obtain energy savings in many other parts in the processor. The explanation is that the fetch unit often runs substantially ahead of execution, bringing in instructions to different stages in the processor that may never be executed. We have found, that although the degree of Instruction Level Parallelism (ILP) of a program tends to vary over time, it can be statically predicted by the compiler with considerable accuracy. Our Instructions Per Clock (IPC) prediction scheme is using a dependence-testing-based analysis and simple heuristics, to guide a front-end fetch-throttling mechanism. We develop the necessary architecture support and include its power overhead. We perform experiments over a wide number of architectural configurations, using SPEC2000 applications. Our results are very encouraging: we obtain up to 15% total energy savings in the processor with generally little performance degradation. In fact, in some cases our intelligent throttling scheme even increases performance. - AJ KleinOsowski, D.J. Lilja. "MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research." Volume 1, May 2002. Computer architects must determine how to most effectively use finite computational resources when running simulations to evaluate new architectural ideas. To facilitate efficient simulations with a range of benchmark programs, we have developed the MinneSPEC input set for the SPEC CPU 2000 benchmark suite. This new workload allows computer architects to obtain simulation results in a reasonable time using existing simulators. While the MinneSPEC workload is derived from the standard SPEC CPU 2000 workload, it is a valid benchmark suite in and of itself for simulation-based research. MinneSPEC also may be used to run large numbers of simulations to find ``sweet spots'' in the evaluation parameter space. This small number of promising design points subsequently may be investigated in more detail with the full SPEC reference workload. In the process of developing the MinneSPEC datasets, we quantify its differences in terms of function-level execution patterns, instruction mixes, and memory behaviors compared to the SPEC programs when executed with the reference inputs. We find that for some programs, the MinneSPEC profiles match the SPEC reference dataset program behavior very closely. For other programs, however, the MinneSPEC inputs produce significantly different program behavior. The MinneSPEC workload has been recognized by SPEC and is distributed with Version 1.2 and higher of the SPEC CPU 2000 benchmark suite. - H. Vandierendonck, K. De Bosschere. "An Address Transformation Combining Block- and Word-Interleaving." Volume 1, May 2002. As future superscalar processors employ higher issue widths, an increasing number of load/store-instructions needs to be executed each cycle to sustain high performance. Multi-bank data caches attempt to address this issue in a cost-effective way. A multi-bank cache consists of multiple cache banks that each support one load/store-instruction per clock cycle. The interleaving of cache blocks over the banks is of primary importance. Two common choices are block-interleaving and word-interleaving. Although word-interleaving leads to higher IPC, it is more expensive to implement than block-interleaving since it requires the tag array of the cache to be multi-ported. By swapping the bits in the effective address that are used by word-interleaving with those used by block-interleaving, it is possible to implement a word-interleaved cache with the same cost, cycle time and power consumption of a block-interleaved cache. Because this makes the L1 data cache blocks sparse, additional costs are incurred at different levels of the memory hierarchy. ----------------------------------------------------------- 17th Annual International Parallel and Distributed Processing Symposium IPDPS 2003 http://www.ipdps.org/ DATES: April 22-26, 2003 LOCATION: Nice, France General Co-Chairs: Michel Cosnard, , and Allan Gottlieb, Program Chair: Jack Dongarra General Contact: David A. Bader In 2003, IPDPS will follow its accustomed format, providing a forum for engineers and scientists from around the world to present their latest research findings in the fields of parallel processing and distributed computing. Sponsored by the IEEE Computer Society Technical Committee on Parallel Processing, in cooperation with ACM SIGARCH, IEEE Computer Society Technical Committee on Computer Architecture, and IEEE Computer Society Technical Committee on Distributed Processing, and hosted by INRIA Sophia Antipolis, CNRS & University of Nice. ------------------------------------------------------------------------ ************************************************************************* IPDPS 2003 International Parallel and Distributed Processing Symposium http://www.ipdps.org/ CALL FOR PAPERS Submission Deadline: October 4, 2002 ************************************************************************* For more information e-mail: info@ipdps.org 17th Annual International Parallel & Distributed Processing Symposium IPDPS 2003 Tuesday, 22 April -- Saturday, 26 April, 2003 Nice Acropolis Convention Center Nice, France =20 Sponsored by: IEEE Computer Society Technical Committee on Parallel Processing In cooperation with: ACM SIGARCH IEEE Computer Society Technical Committee on Computer Architecture (TCCA) IEEE Computer Society Technical Committee on Distributed Processing (TCDP) (Hosted by INRIA Sophia Antipolis, CNRS & University of Nice ) IPDPS 2003 CALL FOR PARTICIPATION In 2003, IPDPS will follow its accustomed format, providing a forum for engineers and scientists from around the world to present their latest research findings in the fields of parallel processing and distributed computing. Workshops and tutorials serve as the "book-end" events on the first and last days. Note that in Nice the beginning day will be Tuesday the 22nd and the final day of IPDPS will be Saturday the 26th. The three intervening days open with addresses by invited speakers and focus on the presentation of contributed papers in technical sessions organized around symposium topics of interest. Particularly hot topics are further explored via panel discussions, as well as other ad hoc meetings and discussions throughout the week. Details on local accommodations as well as travel tips will be posted on the Web before the end of the year, so you are encouraged to regularly check the IPDPS Web site at www.ipdps.org for updates. General email inquiries should be addressed to . GENERAL CO-CHAIRS Michel Cosnard, Universite' de Nice & INRIA Sophia Antipolis, France Allan Gottlieb, New York University & NEC Research Institute, GENERAL VICE CO-CHAIRS Luc Bouge', ENS Cachan & IRISA, Rennes, France Charles Weems, University of Massachusetts at Amherst, WORKSHOPS --------- Workshops are an opportunity to explore special topics, and running a workshop in association with IPDPS offers many advantages. The 18 workshops held at IPDPS 2002 are already planning for continuation in 2003 and several more have been proposed. Contact General Vice Co-Chair Charles Weems for details on workshop proposals. To obtain more information on an individual IPDPS workshop, go to the IPDPS Web site at www.ipdps.org. Each workshop has its own requirements and schedule for submissions and all are linked from the IPDPS Web site. WORKSHOPS AT IPDPS 2003 ----------------------- * Heterogeneous Computing Workshop (HCW) * Workshop on Parallel and Distributed Real-Time Systems (WPDRTS) * Workshop on High-Level Parallel Programming Models & Supportive Environments (HIPS) * Workshop on Java for Parallel and Distributed Computing (JAVAPDC) * Workshop on Parallel and Distributed Image Processing, Video Processing, and Multimedia (PDIVM) * Workshop on Advances in Parallel and Distributed Computational Models (APDCM) * Reconfigurable Architectures Workshop (RAW) * Workshop on Communication Architecture for Clusters (CAC) * NSF Next Generation Systems Program Workshop (NSFNGS) * International Workshop on High Performance Computational Biology (HiCOMB) * International Workshop on Wireless, Mobile, and Ad Hoc Networks (WMAHN) * Workshop on Fault-Tolerant Parallel and Distributed Systems (FTPDS) * Workshop on Nature Inspired Distributed Computing (NIDISC) * Workshop on Formal Methods for Parallel Programming (FMPP) * Workshop on Internet Computing and E-commerce (ICEC) * Workshop on Parallel and Distributed Scientific and Engineering Computing with Applications (PDSECA) * Workshop on Massively Parallel Processing (WMPP) * Workshop on Performance Modeling, Evaluation, and Optimization of Parallel and Distributed Systems (PMEO) * Workshop on Massively Parallel Computer Aided Surgery (MPCAS) INDUSTRIAL-TRACK/COMMERCIAL EXHIBITS ------------------------------------ Industrial track presentations are an excellent opportunity for companies to showcase new technologies and to enter into the lively discussions encouraged at IPDPS. Paired with three days of "walk-up-and-talk" exhibits, industrial researchers can promote awareness about their recent technological advances and obtain feedback from a diverse audience. Industrial sponsors are linked from the IPDPS home page, giving them several months of visibility, and papers presented become part of the IPDPS proceedings. Proposals for innovative ways to showcase vendor products or to provide sponsor benefits in lieu of exhibiting are also encouraged. Companies interested in participating should contact one of the Industrial Track Co-Chairs by October 20, 2002: Isabelle Attali or Kiran Bondalapati . TUTORIALS --------- Proposals are solicited for organizing full or half-day tutorials. Interested individuals should submit a proposal by October 20, 2002 to the Tutorials Chair Patricia Teller . Contact her for details prior to submitting your proposal. IPDPS 2003 - IMPORTANT DATES 15 June 2002 Workshop Proposals Due 4 October 2002 Manuscripts Due 20 October 2002 Tutorial Proposals Due 20 October 2002 Industrial Track Submissions Due 20 December 2002 Review Decisions Mailed 24 January 2003 Print Ready Paper Due CALL FOR PAPERS Authors are invited to submit manuscripts that demonstrate original unpublished research in all areas of parallel and distributed processing including development of experimental or commercial systems. Topics of interest include but are not limited to: 1. Parallel and distributed algorithms, including communication and synchronization protocols. 2. Applications of parallel and distributed computing, including web applications, peer-to-peer computing, grid computing and scientific applications. 3. Parallel and distributed architectures, including signal and image processors, network processors, other special purpose processors, nontraditional processor technologies, network and interconnect architecture, and performance modeling and evaluation. 4. Parallel and distributed software, including parallel programming languages and compilers, operating systems, runtime, middleware, libraries, programming environments and tools for parallel and distributed computing. BEST PAPER AWARDS ----------------- Awards will be given for the best paper in each of the four conference topics. The selected papers will also be considered for possible publication in a special issue of the Journal of Parallel and Distributed Computing. WHAT TO SUBMIT -------------- Submitted manuscripts may not exceed 12 single-spaced pages of text using 12-point size type on 8.5x11 inch pages. References, figures, tables, etc. may be included in addition to the twelve pages of text. Hardcopy submissions will be accepted, but files in either PostScript (level 2) or PDF format are strongly encouraged. (Note: Authors need to make sure that the electronically submitted files will print on a PostScript printer that uses 8.5x11 inch paper.) Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the conference attendees. Submitted papers may not have appeared in or be considered for another conference. Submission procedures are available via Web access at www.ipdps.org. For those who have only e-mail access, send an e-mail message to for an automatic reply that will contain detailed instructions for submission of manuscripts. If no electronic access is available, contact the program chair at the address given below. All manuscripts will be reviewed. Manuscripts must be received by October 4, 2002 at 12 Noon EST. (Note: Authors will be granted an automatic extension of up to 1 week (168 hours) without making a special request. However, no further extensions will be granted.) Submissions received after the due date or exceeding the length limit may not be considered. Notification of review decisions will be mailed by December 20, 2002. Camera-ready papers will be due January 24, 2003. IPDPS 2003 Proceedings for both contributed papers and workshops will be published by the IEEE Computer Society Press on CD-ROM and will be distributed at the Symposium along with a hard copy volume of abstracts. PROGRAM CHAIR Jack Dongarra University of Tennessee 1122 Volunteer Blvd Knoxville, TN 37996-3450 USA PROGRAM VICE-CHAIRS * ALGORITHMS Yves Robert, Ecole Normale Supe'rieure de Lyon * APPLICATIONS David Walker, Cardiff University * ARCHITECTURES Josep Torrellas, University of Illinois at Urbana-Champaign * SOFTWARE John Mellor-Crummey, Rice University =20 PROGRAM COMMITTEE Giovanni Aloisio, University of Lecce, Italy Eduard Ayguade, Centre Europeu de Parallelisme de Barcelona, Spain Mark Baker, University of Portsmouth, UK Laxmi Bhuyan, University of California, Riverside Henri Casanova, University of California, San Diego Serge Chaumette, University of Bordeaux, France Jong-Doek Choi, IBM Research Marcelo Cintra, University of Edinburgh, UK Simon Cox, Southampton University, UK Chita Das, Pennsylvania State University Peter Dickman, University of Glasgow, UK John Drake, Oak Ridge National Laboratory Thomas Fahringer, University of Vienna, Austria Wu-Chun Feng, Los Alamos National Laboratory Renato Figueiredo, Northwestern University Robert Fowler, Rice University Manoj Franklin, University of Maryland, College Park Guang Gao, University of Delaware Martyn Guest, Daresbury Laboratory, UK Yike Guo, Imperial College, UK John Gurd, University of Manchester, UK Mark Heinrich, Cornell University Jeffrey Hollingsworth, University of Maryland Jesu's Labarta, Technical University of Catalonia, Spain Domenico Laforenza, CNUCE-CNR Pisa, Italy Evangelos Markatos, ICS-FORTH & University of Crete, Greece Jose Moreira, IBM Research Michael O'Boyle, University of Edinburgh, Scotland D.K. Panda, Ohio State University Timothy Pinkston, University of Southern California Omer Rana, Cardiff University, UK Michael M. Resch, High Performance Computing Center, Stuttgart, Germany Wojciech Rytter, University of Liverpool, UK Yousef Saad, University of Minnesota Pascal Sainrat, Universite' Paul Sabatier, Toulouse, France Rizos Sakellariou, University of Manchester, UK Andre' Schiper, Ecole Polytechnique Fe'de'rale de Lausanne, Switzerland Jennifer Schopf, Northwestern University Bernard Schutz, MPI for Gravitational Physics, Germany Steve Scott, Cray Research Leonel Seabra de Sousa, Instituto Superior Te'cnico, Portugal Per Stenstrom, Chalmers University, Sweden Quentin F. Stout, University of Michigan Thomas Stricker, ETH Zurich, Switzerland Alan Sussman, University of Maryland Sivan Toledo, Tel-Aviv University, Israel Dean Tullsen, University of California, San Diego Mateo Valero, Universitat Polite`cnica de Catalunya, Spain Jeffrey Vetter, Lawrence Livermore National Laboratory Jennifer Welch, Texas A&M University Marianne Winslett, University of Illinois at Urbana-Champaign Sudha Yalamanchilli, Georgia Tech Tuesday, 22 April 2003 -- Saturday, 26 April 2003 17th International Parallel & Distributed Processing Symposium Join us in Nice on the French Riviera! IPDPS 2003 -- to be held in Nice, France -- will be hosted by INRIA, CNRS and the University of Nice. INRIA is the French Institute for research & development in information, communication, science and technology, and includes the Sophia-Antipolis INRIA Research Unit, which is located 20 miles from Nice and is neighbor to a major concentration of French high-tech industries and research centers. Similar to the American NSF, the CNRS sponsors research in high performance computing and networking. In this domain, the CNRS connects over 80 research groups in France, including the I3S laboratory, which operates in cooperation with the University of Nice Sophia Antipolis. Both INRIA and CNRS are vitally interested in promoting international exchange, making them ideal hosts for the 17th International Parallel & Distributed Processing Symposium. The Nice setting offers state-of-the-art meeting facilities in the Acropolis Convention Center, and there is a wide assortment of hotel accommodations within walking distance. Located between Cannes and Monte Carlo on the French Riviera, Nice provides a sidewalk cafe' and beach atmosphere to complement the technical resources available to IPDPS through the nearby Sophia-Antipolis INRIA Research Unit. Make sure your passports are up to date and keep next April open for your travel to the French Riviera. Visit the IPDPS Web site at www.ipdps.org for further information and regular updates on travel & accommodations. IPDPS 2003 ORGANIZATION GENERAL CO-CHAIRS * Michel Cosnard Universite' de Nice & INRIA Sophia Antipolis, France * Allan Gottlieb New York University & NEC Research Institute GENERAL VICE CO-CHAIRS Luc Bouge', ENS Cachan & IRISA, Rennes, France Charles Weems, University of Massachusetts at Amherst PROGRAM CHAIR Jack Dongarra, University of Tennessee STEERING CO-CHAIRS Viktor K. Prasanna, University of Southern California George Westrom, Future Scientists & Engineers of America TUTORIALS CHAIR Patricia J. Teller, University of Texas at El Paso INDUSTRIAL TRACK CO-CHAIRS Isabelle Attali, INRIA Sophia Antipolis, France Kiran Bondalapati, Advanced Micro Devices, Inc. PROCEEDINGS CHAIR Jose Nelson Amaral, University of Alberta, Canada FINANCE CHAIR Bill Pitts, Toshiba America Information Systems, Inc. LOCAL ARRANGEMENTS CO-CHAIRS Susamma Barua, California State University, Fullerton Francoise Baude, Universite' de Nice Sophia Antipolis, France Marie-He'le`ne Zeitoun, INRIA Sophia Antipolis, France =20 PRODUCTION CHAIR Sally Jelinek, Electronic Design Associates, Inc. PUBLICITY CO-CHAIRS David A. Bader, University of New Mexico Serge Chaumette, Universite' de Bordeaux, France =20 PUBLICITY COORDINATORS * Asia/Far East Satoshi Sekiguchi National Institute of Advanced Industrial Science & Technology, Japan * Australia/New Zealand Albert Zomaya University of Sydney * Central/South America Ricardo Correa Universidade Brazil * Europe/Africa Thomas Ludwig University of Heidelberg * Middle East Skevos Evripidou University of Cyprus STEERING COMMITTEE K. Mani Chandy, California Institute of Technology Ali R. Hurson, Pennsylvania State University Joseph JaJa,University of Maryland F. Tom Leighton, MIT Jose' Rolim, University of Geneva Sartaj Sahni, University of Florida Behrooz Shirazi, University of Texas at Arlington H.J. Siegel, Colorado State University Hal Sudborough, University of Texas at Dallas Steering Committee 2003 membership also includes the general = co-chairs, program chairs, and vice general co-chairs from 2002, 2003, & 2004. ADVISORY COMMITTEE Said Bettayeb, University of South Alabama (USA) Michael J. Flynn, Stanford University (USA) Friedhelm Meyer auf der Heide, University of Paderborn (Germany) Louis O. Hertzberger, University of Amsterdam (The Netherlands) Richard Karp, University of California, Berkeley (USA) Jan van Leeuwen, University of Utrecht (The Netherlands) David R. Martinez, MIT Lincoln Laboratory (USA) Kurt Mehlhorn, Max Planck Institute (Germany) Gary Miller, Carnegie Mellon University (USA) Juerg Nievergelt, ETH Zurich (Switzerland) Charles L. Seitz, Myricom, Inc. (USA) Ioannis Tollis, University of Texas, Dallas (USA) Leslie Valiant, Harvard University (USA) Paolo Zanella, E.B.I., Cambridge (UK) --- IPDPS 2003 - IMPORTANT DATES 15 June 2002 Workshop Proposals Due 4 October 2002 Manuscripts Due 20 October 2002 Tutorial Proposals Due 20 October 2002 Industrial Track Submissions Due 20 December 2002 Review Decisions Mailed 24 January 2003 Print Ready Paper Due David A. Bader Office: 505-277-6724 Assistant Professor and Regents' Lecturer FAX: 505-277-1439 Electrical and Computer Engineering Department University of New Mexico dbader@eece.unm.edu Albuquerque, NM 87131 http://www.eece.unm.edu/~dbader ------------------------------------------------------------------------ * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members, send an email to tcca@ele.uri.edu * To subscribe/unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: subscribe/unsubscribe -----------------------------------------------------------------------